technical data 276 octal 3-state inverting buffer/line driver/line receiver high-performance silicon-gate cmos the in74hct240a is identical in pinout to the ls/als240. the in74hct240a may be used as a level converter for interfacing ttl or nmos outputs to high speed cmos inputs. this octal inverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus- oriented systems. the device has inverting outputs and two active-low output enables. ? ttl/nmos compatible input levels ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 4.5 to 5.5 v ? low input current: 1.0 a in74hct240a ordering information in74hct240an plastic IN74HCT240ADW soic t a = -55 to 125 c for all packages function table inputs outputs enable a, enable b a,b ya,yb llh lhl hxz x = don?t care z = high impedance logic diagram pin 20=v cc pin 10 = gnd pin assignment
in74hct240a 277 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c t r , t f input rise and fall time (figure 1) 0 500 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
in74hct240a 278 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to -55 c 85 c 125 c unit v ih minimum high-level input voltage v out =0.1 v ? i out ? 20 a 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 v v il maximum low - level input voltage v out = v cc -0.1 v ? i out ? 20 a 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 v v oh minimum high-level output voltage v in = v il ? i out ? 20 a 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 v v in =v il ? i out ? 6.0 ma 4.5 3.98 3.84 3.7 v ol maximum low-level output voltage v in =v ih ? i out ? 20 a 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih ? i out ? 6.0 ma 4.5 0.26 0.33 0.4 i in maximum input leakage current v in =v cc or gnd 5.5 0.1 1.0 1.0 a i oz maximum three state leakage current output in high-impedance state v in = v il or v ih v out =v cc or gnd 5.5 0.5 5.0 10.0 a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 a 5.5 4.0 40 160 a ? i cc additional quiescent supply current v in = 2.4 v, any one input v in =v cc or gnd, other inputs -55 c25 c to 125 c ma i out =0 a 5.5 2.9 2.4 note: total supply current = i cc + ? i cc
in74hct240a 279 ac electrical characteristics (v cc =5.0 v 10%, c l =50pf,input t r =t f =6.0 ns) guaranteed limit symbol parameter 25 c to -55 c 85 c 125 c unit t plh , t phl maximum propagation delay, a to ya or b to yb (figures 1 and 3) 20 25 30 ns t plz , t phz maximum propagation delay, output enable to ya or yb (figures 2 and 4) 28 35 42 ns t pzh , t pzl maximum propagation delay, output enable to ya or yb (figures 2 and 4) 25 31 38 ns t tlh , t thl maximum output transition time, any output (figures 1 and 3) 12 15 18 ns c in maximum input capacitance 10 10 10 pf c out maximum three-state output capacitance (output in high-impedance state) 15 15 15 pf power dissipation capacitance (per enable output) typical @25 c,v cc =5.0 v c pd used to determine the no-load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 55 pf figure 1. switching waveforms figure 2. switching waveforms
in74hct240a 280 figure 3. test circuit figure 4. test circuit expanded logic diagram (1/8 of the device)
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